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System-on-chip test architectures: nanometer design for testability

By: Contributor(s): Material type: TextTextPublication details: Boston Morgan Kaufmann 2008Edition: Description: xxxiii, 856pISBN:
  • 9780123739735
ISSN:
Subject(s): DDC classification:
  • 621.9
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University Library
Cochin University of Science and Technology
Kochi-682 022, Kerala, India