Wang, Laung-Terng <br/><br/>
System-on-chip test architectures: nanometer design for testability 

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 - Boston  Morgan Kaufmann  2008 
 - xxxiii, 856p.   
<br/><br/>   
<br/><br/><label>ISBN: </label>9780123739735 
<br/><br/><label>ISSN: </label>
<br/><br/><label>Subjects--Index Terms: </label>Systems on a chip-Testing  Integrated circuits- very large scale integration- Testing 
<br/><br/><label>Dewey Class. No.: </label>621.9